March 7, 2017

A Practical Guide for SystemVerilog Assertions by Srikanth Vijayaraghavan

By Srikanth Vijayaraghavan

SystemVerilog language comprises 3 very particular components of constructs - layout, assertions and testbench. Assertions upload an entire new measurement to the ASIC verification procedure. Assertions supply a greater option to do verification proactively. routinely, engineers are used to writing verilog attempt benches that aid simulate their layout. Verilog is a procedural language and is especially restricted in services to address the advanced Asic's outfitted this present day. SystemVerilog assertions (SVA) are a declarative and temporal language that gives first-class keep an eye on through the years and parallelism. this gives the designers a really powerful instrument to resolve their verification difficulties. whereas the language is equipped strong, the considering is particularly various from the user's viewpoint in comparison to straightforward verilog language. the idea that remains to be very new and there's now not sufficient services within the box to undertake this system and prevail. whereas the language has been outlined rather well, there is not any useful advisor that indicates the way to use the language to resolve actual verification difficulties. This e-book often is the sensible advisor that might aid humans to appreciate this new method.

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Property p9; @(posedge elk) endproperty = > b; a9 : assert property{p9); 1. Introduction 27 to SVA Figure 1-12 shows how the assertion a9 responds in a simulation. Table 1-6 summarizes the sampled values of signal "a" and signal "b" and the status of the assertion. Note that this assertion starts in the current clock cycle and succeeds in the next clock cycle if it is a real success. Similarly, if there is a valid start for the property (high on signal "a"), the property fails in the next clock cycle if signal "b" is not high in that clock cycle.

Sequence s 3 _ l i b _ i n s t l ; S3_lib{reql, req2); 1. Introduction to SVA 19 endsequence Some of the common properties that are normally present in designs can be developed as a library and re-used. For example, one-hot state machine checks, parity checks, etc. are good candidates for a checker library. 10 Sequences with timing relationsliip Simple boolean expressions are checked on every clock edge. In other words, they are simple combinational checks. A lot of times, we are interested in checking events that take several clock cycles to complete.

Introduction to SVA 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 * jiTLTLJiJirLJTJinnjiJ^^ ns\ alSa al5b • IN n LLi Figure 1-18. Waveform for SVA checker using "ended" The first failure for assertion a 15a happens at clock cycle 5. A valid starting point is detected when signal "a" is detected high on a given positive clock edge and is followed by a high on signal "b" one clock cycle later (clock cycle 6). This leads to checking the consequent and since signal "c" is not high after one clock cycle, the check fails at clock cycle 7.

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